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3-1 tm file number 4642.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 HI3256 8-bit, 120msps, flash a/d converter the HI3256 is an 8-bit, high-speed, ?sh analog-to-digital converter optimized for high speed, low power, and ease of use. with a 120msps encode rate capability and full-power analog bandwidth of 250mhz, this component is ideal for applications requiring the highest possible dynamic performance. to minimize system cost and power dissipation, only a +5v power supply is required. the HI3256 clock input interfaces directly to ttl, ecl or pecl logic and will operate with single- ended inputs. the user may select 16-bit demultiplexed output or 8-bit single channel digital outputs. the demultiplexed mode interleaves the data through two 8-bit channels at 1 / 2 the clock rate. operation in demultiplexed mode reduces the speed and cost of external digital interfaces, while allowing the a/d converter to be clocked to the full 120msps conversion rate. fabricated with an advanced bipolar process, the HI3256 is provided in a space-saving 48-lead lqfp surface mount plastic package and is speci?d over the -20 o c to 75 o c temperature range. features differential linearity error. . . . . . . . . . . . . . . . . . 0.5 lsb integral linearity error . . . . . . . . . . . . . . . . . . . . 0.5 lsb low input capacitance . . . . . . . . . . . . . . . . . . . . . . . 10pf wide analog input bandwidth . . . . . . . . . . . . . . . 250mhz low power consumption . . . . . . . . . . . . . . . . . . . 500mw output voltage control function (voclp pin) 1:2 demultiplexed output pin internal 1 / 2 frequency divider circuit (w/reset function) clk/2 clock output compatible with pecl, ecl and ttl digital input levels direct replacement for sony cxa3256r applications lcd/pdp monitors and projectors (rgb video) digital oscilloscopes digital communications (qpsk, qam) magnetic recording (prml) pinout HI3256 (lqfp) top view ordering information part number temp. range ( o c) package pkg. no. HI3256jcq -20 to 75 48 ld lqfp q48.7x7-s 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pbd3 pbd2 pbd1 pbd0 dgnd2 dv cc2 dv cc1 dgnd1 pad7 pad6 pad5 pad4 dv ee3 v rb agnd v rm1 av cc av cc v rm3 agnd v rt dgnd3 v in v rm2 resetn/e reset/e resetn/t select1 inv dv cc2 dgnd2 pbd7 pbd6 pbd5 pbd4 clkout clk/e clkn/e clk/t select2 voclp ps dv cc2 dgnd2 pad0 pad1 pad2 pad3 data sheet june 1999
3-2 block diagram 5 8 30 19 31 42 12 dgnd3 dv cc2 dv cc1 inv av cc 11 9 126 65 64 63 2 127 128 129 191 192 193 254 255 6 4 7 reset/e resetn/e resetn/t clkn/e clk/e clk/t v rb v rm1 v in v rm2 v rm3 v rt r1 r/2 r/2 r r r r r r r r r r r r r r/2 delay dq q select1 3 10 45 29 20 32 41 1 dv ee3 dgnd2 dgnd1 select1 43 18 17 16 34 35 36 37 38 39 40 (msb) pbd7 pbd6 pbd5 pbd4 pbd3 pbd2 pbd1 p1d0 (msb) pad6 pad5 pad4 pad3 pad2 pad1 pad0 clkout (lsb) pad7 (lsb) 6-bit latch and encoder encoder 6 bits 6 bits 6 bits 6 bits (8 bits) 8 bits latchb ttlout 21 22 23 24 25 26 27 28 ttlout 33 1 46 48 47 2 15 13 14 agnd latcha r/2 44 select2 voclp ps HI3256
3-3 absolute maximum ratings t a = 25 o c thermal information supply voltage (av cc , dv cc1 , dv cc2 ) . . . . . . . . . . -0.5v to +7.0v (dgnd3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v (dv ee3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0v to +0.5v (dgnd3 - dv ee3 ) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v analog input voltage (v in ). . . . . . . . . . . . . . . . . v rt - 2.7v to av cc reference input voltage (v rt ). . . . . . . . . . . . . . . . . +2.7v to av cc (v rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v in - 2.7v to av cc (|v rt - v rb |) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5v digital input voltage pecl/ecl . . . . . . . . . . . . . . . . . . . dv ee3 - 0.5 to dgnd3 + 0.5 ttl . . . . . . . . . . . . . . . . . . . . . . . . . dgnd3 - 0.5 to dv cc1 + 0.5 v id (|***/e - ***n/e| (note 2)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v thermal resistance (typical, note 1) ja ( o c/w) lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (lead tips only) recommended operating conditions with a single power supply min typ max supply voltage dv cc1 , dv cc2 , av cc . . . . . . . . . . . . . . . +4.75 +5.0 +5.25v dgnd1, dgnd2, agnd . . . . . . . . . . . . . -0.05 0 +0.05v dgnd3. . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25v dv ee3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05v analog input voltage (v in ). . . . . . . . . . . . . . v rb -v rt reference input voltage v rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1v v rb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.4 - +2.6v |v rt - v rb |. . . . . . . . . . . . . . . . . . . . . . . . +1.5 - +2.1v digital input voltage pecl (***/e) v ih . . . . . . . . . . . . . . dv ee3 + 1.5 dgnd3 pecl (***/e) v il . . . . . . . . . . . . . . . dv ee3 + 1.1 v ih - 0.4v ttl (***/t, inv) v ih . . . . . . . . . . . . . . . . . +2.0v - - ttl (***/t, inv) v il . . . . . . . . . . . . . . . . . - - +0.8v other (select1/2) v ih . . . . . . . . . . . . . . - dv cc1 - other (select1/2) v il . . . . . . . . . . . . . . - dgnd1 - v id (note 2) (|***/e- ***n/e|) . . . . . . . . . . +0.4 +0.8 - max conversion rate (f c , straight mode) . . . 100 - - msps max conversion rate (f c , dmux mode) . . . . 120 - - msps ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . -20 o c to 75 o c with dual power supplies min typ max supply voltage dv cc1 , dv cc2 , av cc . . . . . . . . . . . . . . . +4.75 +5.0 +5.25v dgnd1, dgnd2, agnd . . . . . . . . . . . . . -0.05 0 +0.05v dgnd3. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05v dv ee3 . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75v analog input voltage (v in ). . . . . . . . . . . . . . v rb -v rt reference input voltage v rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1v v rb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.4 - +2.6v |v rt - v rb |. . . . . . . . . . . . . . . . . . . . . . . . +1.5 - +2.1v digital input voltage pecl/ecl v ih . . . . . . . . . . . . . . . . . . . . . . . dv ee3 + 1.5 dgnd3 pecl/ecl v il . . . . . . . . . . . . . . . . . . . . . . . dv ee3 + 1.1 v ih - 0.4 ttl (***/t, inv) v ih . . . . . . . . . . . . . . . . . 2.0 - - ttl (***/t, inv) v il . . . . . . . . . . . . . . . . . - - +0.8v other (select1/2) v ih . . . . . . . . . . . . . . - dv cc1 - other (select1/2) v il . . . . . . . . . . . . . . - dgnd1 - v id (note 2) (|***/e- ***n/e|) . . . . . . . . . . +0.4 0.8 - max conversion rate (f c , straight mode) . . . 100 - - msps max conversion rate (f c , dmux mode) . . . . 120 - - msps ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . -20 o c to 75 o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. notes: 1. ja is measured with the component mounted on an evaluation pc board in free air. 2. v id : input voltage differential. electrical speci?ations dv cc1 , 2 , av cc , dgnd3 = +5v, dgnd1, 2, agnd, dv ee3 = 0v, v rt = 4v, v rb = 2v, t a = 25 o c parameter test conditions min typ max units resolution - 8 - bits dc characteristics integral linearity error, inl v in = 2v p-p , f c = 5msps - - 0.5 lsb differential linearity error, dnl - - 0.5 lsb analog input analog input capacitance, c in v in = +3.0v, +0.07v rms -10-pf analog input resistance, r in 72040k ? analog input current, i in 0 100 285 a HI3256
3-4 reference input reference resistance (note 3), r ref 400 600 740 ? reference current (note 4), i ref 2.7 3.3 5.0 ma offset voltage v rt side, eot 6 8 10 mv offset voltage v rb side, eob 0 1.5 3 mv digital input (pecl/ecl) digital input voltage: high, v ih dv ee3 + 1.5 - dgnd3 v digital input voltage: low, v il dv ee3 + 1.1 - v ih - 0.4 v threshold voltage, v th - dgnd3 - 1.2 - v digital input current: high, i ih v ih = dgnd3 - 0.8v -50 - +50 a digital input current: low, i il v il = dgnd3 - 1.6v -50 - 0 a digital input capacitance - - 5 pf digital input (ttl) digital input voltage: high, v ih 2.0 - - v digital input voltage: low, v il - - 0.8 v threshold voltage, v th - 1.5 - v digital input current: high, i ih v ih = 3.5v -10 - 0 a digital input current: low, i il v il = 0.2v -20 - 0 a digital input capacitance - - 5 pf digital output (ttl) digital output voltage: high, v oh i oh = -2ma 2.4 - - v digital output voltage: low, v ol i ol = 1ma - - 0.5 v switching characteristics maximum conversion rate, f c demux mode 120 - - msps aperture jitter, t aj -10-ps sampling delay, t ds 1.2 1.4 1.6 ns clock high pulse width, t pw1 clk 3.0 - - ns clock low pulse width, t pw0 clk 4.5 - - ns reset signal setup time, t rs resetn-clk 1.0 - - ns reset signal hold time, t rh resetn-clk -0.5 - - ns clkout output delay, t dclk c l = 5pf 3.0 4.5 7.0 ns data output delay (note 5), t do1 t do2 demux mode (c l = 5pf) - t + 0.5 - ns (c l = 5pf) 3.5 5.0 7.0 ns output rise time, t r 0.8 to 2.0v (c l = 5pf) - 1 - ns output fall time, t f 0.8 to 2.0v (c l = 5pf) - 1 - ns dynamic characteristics input bandwidth v in = 2v p-p , -3db 250 - - mhz s/n ratio f c = 120msps, f in = 1khz full scale, demux mode -46-db f c = 120msps, f in = 29.999mhz full scale, demux mode -42-db error rate (note 6) f c = 120msps, f in = 1khz full scale, demux mode, error > 16 lsb --10 -12 tps f c = 120msps, f in = 29.999mhz full scale, demux mode, error > 16 lsb --10 -9 tps f c = 100msps, f in = 24.999mhz full scale, straight mode, error > 16 lsb --10 -9 tps power supply operating (ps = 1) total supply current, i cc + i ee 70 98 140 ma electrical speci?ations dv cc1 , 2 , av cc , dgnd3 = +5v, dgnd1, 2, agnd, dv ee3 = 0v, v rt = 4v, v rb = 2v, t a = 25 o c (continued) parameter test conditions min typ max units HI3256
3-5 av cc pin supply current, ai cc 45 - 87 ma dv cc1 pin supply current, dicc1 20 - 36 ma dv cc2 pin supply current, dicc2 5 - 15 ma dgnd3 pin supply current, i ee 0.5 - 1.5 ma power consumption, pd *6 400 500 700 mw power supply in power saving mode (ps = 0) total supply current, ps i cc + i ee --5ma av cc pin supply current, ps ai cc - - 1.5 ma dv cc1 pin supply current, ps dicc1 - - 1.5 ma dv cc2 pin supply current, ps dicc2 - - 1.5 ma dgnd3 pin supply current, ps i ee - - 0.5 ma power consumption, ps pd *6 - - 25 mw notes: 3. r ref : resistance value between v rt and v rb . 4. . 5. . 6. t he unit of measure tps: times per sample. 7. . electrical speci?ations dv cc1 , 2 , av cc , dgnd3 = +5v, dgnd1, 2, agnd, dv ee3 = 0v, v rt = 4v, v rb = 2v, t a = 25 o c (continued) parameter test conditions min typ max units i ref v rt v rb r ref ----------------------------- = t 1 f c ----- = p d i cc i ee + () v cc ? v rt v rb () 2 v ref ------------------------------------- + = timing diagrams figure 1. demux mode timing chart (select1 = v cc ) n - 1 t ds t pw1 t pw0 n n + 1 t d02 n + 2 n + 3 n + 2 n 2v 0.8v n - 2 t dclk 2v 0.8v 2v 0.8v n - 1 2v 0.8v n + 1 t d01 t + 1ns n + 3 reset pulse clk out pbd0 to d7 pad0 to d7 clk v in t t pwr HI3256
3-6 figure 2. straight mode timing chart (select1 = gnd) figure 3. pecl switching level timing diagrams (continued) n - 1 n n + 1 n + 2 n + 3 t ds t pw1 t pw0 n - 4 2.0v 0.8v 2.0v 0.8v n - 5 n - 3 n - 4 n - 2 n - 3 n - 1 n - 2 n n - 1 t d02 8ns 2.0v 0.8v t dclk reset pulse clk out (clk is inverted and output) pbd0 to d7 pad0 to d7 clk v in t v id dgnd3 v ih (max) v il v th (dgnd3 - 1.2v) v ih v il (min) pin descriptions pin no symbol i/o typical voltage level equivalent circuit description 3, 10 agnd gnd analog ground. separated from the digital ground. 5, 8 av cc +5v (typ) analog power supply. separated from the digital power supply. 20, 29 32, 41 dgnd1 dgnd2 gnd digital ground. 19, 30 31, 42 dv cc1 dv cc2 +5v (typ) digital power supply. 12 dgnd3 +5v (typ) (with a single power supply) digital power supply. apply -5v for pecl and ttl input. gnd (with dual power supplies) 1dv ee3 gnd (with a single power supply) digital power supply. apply -5v for pecl and ttl input. +5v (typ) (with dual power supplies) HI3256
3-7 16 select2 i dv cc1 , dgnd1 or open data output switching. data is output from both pa and pd when left open. if pin is connected to dv cc1 , only pa is used as output with pb high impedance. if pin is connected to dgnd1 , only pb is used as output with pa high impedance. 17 voclp i clamp voltage defines ttl output high level. if left open the high level is ~ 2.8v. 18 ps i ttl power savings pin. when left open or at high level the device operates normally. when set to low level the power saving mode enabled. 13 clk/e i pecl/ecl clock input. 14 clk/ne i clk/e complementary input. when left open, this pin goes to the threshold potential. only clk/e can be used for operation, but complementary input is recommended to attain fast and stable operation. 48 resetn/e i reset input. when the input is set to low level, the built-in clk frequency divider circuit can be reset. 47 reset/e i resetn/e complementary input. when left open, this pin goes to the threshold voltage. only resetn/e can be used for operation. 15 clk/t i ttl clock input. 46 resetn/t i reset input. when left open, this input goes to high level. when the input is set to low level, the built-in clk frequency divider circuit can be reset. 44 inv i ttl data output polarity inversion input. when left open, this input goes to high level. (see table 1; i/o correspondence table). pin descriptions (continued) pin no symbol i/o typical voltage level equivalent circuit description 13 48 dgnd3 dv ee3 47 14 46 15 dv cc1 1.5v or dgnd1 dv ee3 44 45 , 44 dv cc1 dgnd1 dv ee3 HI3256
3-8 45 select1 v cc or ground data output mode selection. (see table 2; operating mode table). 11 v rt i 4.0v (typ) top reference voltage. bypass to agnd with a 1 f tantal capacitor and a 0.1 f chip capacitor. 9v rm3 v rb + (v rt - v rb ) reference voltage mid point. bypass to agnd with a 0.1 f chip capacitor. 7v rm2 v rb + (v rt - v rb ) reference voltage mid point. bypass to agnd with a 0.1 f chip capacitor. 4v rm1 v rb + (v rt - v rb ) reference voltage mid point. bypass to agnd with a 0.1 f chip capacitor. 2v rb i 2.0v (typ) bottom reference voltage. bypass to agnd with a 1 f tantal capacitor and a 0.1 f chip capacitor. 6v in iv rt to v rb analog input. 33 to 40 pbd0 to pbd7 o ttl port 1 side data output. 21 to 28 pad0 to pad7 o port 2 side data output. 43 clkout o clock output. (see table 2; operating mode table). pin descriptions (continued) pin no symbol i/o typical voltage level equivalent circuit description 45 dv cc1 dgnd1 dv ee3 11 9 7 4 2 r2 r/2 r r r r r r r/2 r1 comparator 1 comparator 63 comparator 64 comparator 127 comparator 128 comparator 191 comparator 192 comparator 255 3 4 -- - 2 4 -- - 1 4 -- - 6 av cc dv ee3 comparator av cc agnd v ref 21 33 43 40 28 dv cc2 to to dgnd2 dv ee3 dgnd1 dv cc1 HI3256
3-9 notes on operation the HI3256 is a high-speed a/d converter which is capable of ttl, ecl and pecl level clock input. characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. the power supply and grounding have a profound influence on converter performance. the power supply and grounding method are particularly important during high- speed operation. general points for caution are as follows: - the ground pattern should be as large as possible. it is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. - to prevent interference between agnd and dgnd and between av cc and dv cc , make sure the respective patterns are separated. to prevent a dc offset in the power supply pattern, connect the av cc and dv cc lines at one point each, via a ferrite-bead filter. shorting the agnd and dgnd patterns in one place immediately under the a/d converter improves a/d converter performance. - ground the power supply pins (av cc ,dv cc1 ,dv cc2 , dv ee3 ) as close to each pin as possible with a 0.1 f or larger ceramic chip capacitor. (connect the av cc pin to the agnd pattern and the dv cc1 , dv cc2 , dv ee3 pins to the dgnd pattern). - the digital output wiring should be as short as possible. if the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. the analog input pin v in has an input capacitance of approximately 21pf. to drive the a/d converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit; keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. the v rt and v rb pins must have adequate bypass to protect them from high-frequency noise. bypass them to agnd with approximately 1 f tantal capacitor and, 0.1 f capacitor. at this time, approximately dgnd3 - 1.2v voltage is generated. however, this is not recommended for use as threshold voltage v bb as it is too weak. when the digital input level is pecl level, ***/e pins should be used and ***/t pins left open. when the digital input level is ttl, ***/t pins should be used and iii/e pins left open. table 1. a/d code v in step inv 10 d7 d0 d7 d0 v rt 255 1111111100000000 254 1111111000000001 v rm2 128 1000000001111111 127 0111111110000000 1 0000000111111110 v rb 0 0000000011111111 test circuits figure 4. current consumption measurement circuit figure 5. integral linearity error/differential linearity error measurement circuit v rt v in v rb av cc dv cc1 dv cc2 dgnd2 dgnd1 agnd dgnd3 clk/e dv ee3 4v 1.95v 2v 5mhz pecl a a 5v 5v i cc i ee a < b a > b comparator a8 to a1 b8 to b1 b0 a0 HI3256 buffer controller dvm 000...00 to 111..10 v in 8 ? 8 ? -v +v s2 s1: on when a < b s2: on when a > b s1 - + HI3256
3-10 operating modes the HI3256 has two types of operating modes which are selected with pin 45 (select1). dmux mode (see application circuits, figures 18, 19) set the select1 pin to v cc for this mode. in this mode, the clock frequency is divided by 2 in the ic, and the data is output after being demultiplexed by this 1 / 2 frequency divided clock. the 1 / 2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the clkout pin. when using multiple HI3256 units in parallel in this mode, differences in the start timing of the 1 / 2 frequency divided clock may cause operation as shown in figure 9. as a countermeasure, the HI3256 is equipped with a function which resets the 1 / 2 frequency divided clock. when resetting this clock, the reset pulse must be input to the reset pin. see the timing charts for the reset pulse input timing. the a/d converter can operate at f c (min) = 120msps in this mode. straight mode (see application circuits, figures 20, 21) set the select1 pin to gnd for this mode. in this mode, data output can be obtained in accordance with the clock frequency applied to the a/d converter for applications which use the clock applied to the a/d converter as the system clock. the a/d converter can operate at f c (min) = 100msps in this mode. digital input level and supply voltage settings the logic input level for the HI3256 supports pecl and ttl levels. the power supplies (dv ee3 , dgnd3) for the logic input block must be set to match the logic input (clk and reset signals) level. figure 6. error rate measurement circuit figure 7. sampling delay/aperture jitter measurement circuit note: where (lsb) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter t aj is: figure 8. aperture jitter measurement method test circuits (continued) signal source comparator a > b pulse counter signal source latch + 1 / 8 latch a f c b 8 16 lsb 2v p-p sine wave 4 -1khz v in clk clk f c HI3256 logic analyzer HI3256 v in clk amp 8 1024 samples pecl buffer osc1 : variable osc2 100mhz f r 100mhz v rt v rm2 v rb 129 128 127 126 125 (lsb) ? ? t v in clk v in clk sampling timing fluctuation (= aperture jitter) t aj = / ? ? t ------- ?? ?? = / 256 2 --------- - x2 f ?? ?? . table 2. operating mode operating mode select1 maximum conversion rate data output clock output dmux mode v cc 120msps demultiplexed output 60mbps the input clock is 1 / 2 frequency divided and output at 60mhz. straight mode gnd 100msps straight output 100mbps the input clock is inverted and output at 100mhz. HI3256
3-11 table 3. logic input level and power supply settings digital input level dv ee3 dgnd3 supply voltage application circuits pecl 0v +5v +5v figures 18, 20 ttl 0v +5v +5v figures 19, 21 figure 9. when the reset pulse is not used figure 10. when the reset pulse is used HI3256 clk resetn a HI3256 clk resetn b 8 bits clk clkout data clkout data 8 bits clk HI3256 clk resetn a HI3256 clk resetn b 8 bits clk clkout data clkout data 8 bits clk reset pulse reset pulse typical performance curves figure 11. current consumption vs ambient temperature characteristics figure 12. current consumption vs conversion rate characteristics response 110 75 t a , ambient temperature ( o c) current consumption (ma) 25 -25 105 100 95 90 110 120 f c , conversion rate (msps) current consumption (ma) 60 0 105 100 95 90 f in = -1khz f clk 4 dmux mode c l = 5pf HI3256
3-12 figure 13. analog input current vs analog input voltage characteristics figure 14. reference current vs ambient temperature characteristics figure 15. snr vs input frequency response figure 16. error rate vs conversion rate characteristics figure 17. maximum conversion rate vs ambient temperature characteristics typical performance curves (continued) 100 50 0 234 analog input voltage (v) analog input current ( a) v rt = 4v v rb = 2v 4 3 2 -25 25 75 t a , ambient temperature ( o c) reference current (ma) 50 40 30 20 135103050 input frequency (mhz) snr (db) f c = 120msps 10 -6 10 -7 10 -8 10 -9 10 -10 120 140 160 f c , conversion rate (msps) error rate (tps) f in = f clk 4 -1khz error > 16 lsb 150 160 170 140 130 f c , maximum conversion (msps) -25 25 75 t a , ambient temperature (c o ) f in = f clk 4 -1khz error > 16 lsb error rate: 10 -9 tps HI3256
3-13 application circuits figure 18. dmux pecl input figure 19. dmux ttl input 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 p1d0 to p1d7 8-bit digital data latch dg dg +5v (d) latch p2d0 to p2d7 8-bit digital data 8-bit digital data 8-bit digital data 13 14 15 16 17 18 19 20 21 22 23 24 dg +5v (d) +5v (a) 2v dg ag +5v (a) 4v ag ag +5v (d) pecl - clk pecl reset pulse +5v (d) dg dg ag 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 p1d0 to p1d7 8-bit digital data latch dg dg +5v (d) latch p2d0 to p2d7 8-bit digital data 8-bit digital data 8-bit digital data 13 14 15 16 17 18 19 20 21 22 23 24 dg +5v (d) +5v (a) 2v ag ag +5v (a) 4v ag ag +5v (d) ttl - clk ttl reset pulse +5v (d) dg dg ag HI3256
3-14 figure 20. straight pecl input figure 21. straight ttl input application circuits (continued) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 p1d0 to p1d7 8-bit digital data latch dg dg +5v (d) 8-bit digital data 13 14 15 16 17 18 19 20 21 22 23 24 dg +5v (d) +5v (a) 2v ag ag +5v (a) 4v ag ag pecl - clk +5v (d) dg dg dg pecl - ttl +5v(d) ag 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 p1d0 to p1d7 8-bit digital data latch dg dg +5v (d) 8-bit digital data 13 14 15 16 17 18 19 20 21 22 23 24 dg +5v (d) +5v (a) 2v ag ag +5v (a) 4v ag ag ttl - clk +5v (d) dg dg dg +5v(d) ag HI3256
3-15 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com figure 22. straight mode ttl i/o (when a single power supply is used) application circuits (continued) 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 clk/e clkn/e clk/t nc nc nc dv cc2 dgnd2 p2d0 p2d1 p2d2 p2d3 resetn/e reset/e resetn/t select inv clkout dv cc2 dgnd2 p1d7 p1d6 p1d5 p1d4 p2d4 p2d5 p2d6 p2d7 dgnd1 dv cc1 dv cc2 dgnd2 p1d0 p1d1 p1d2 p1d3 dgnd3 v rt agnd v rm3 av cc v rm2 v in av cc v rm1 agnd v rb dv ee3 + - ag +5v (a) ag ag analog input 1 f + ag 2v ag + 1 f 10 f + short short dg (d) +5v 4v 10 f + ttl clk (lsb) p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 p2d6 (msb) p2d7 (lsb) p1d0 p1d1 p1d2 p1d3 p1d4 p1d5 p1d6 (msb) p1d7 short the analog system and digital system at one point immediately under the a/d converter. see the notes on operation. is the chip capacitor of 0.1 f. + - + - HI3256

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